1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with a stacked memory cell.
2. Description of the Related Art
A Phase-change random Access Memory (PRAM) is formed of a phase-change material such as a chalcogenide alloy that changes into a first of two phases when it is heated and cooled, and changes into a second phase when it is heated and cooled again. Here, the two phases are crystalline and amorphous phases. The PRAM is disclosed in U.S. Pat. Nos. 6,487,113 and 6,480,438. The PRAM has a low resistance value when it becomes crystalline, and a high resistance value when it is amorphous. A logic value can be determined as 0 or 1 according to the resistance value of the PRAM. The crystalline phase of the PRAM corresponds to a set state or has a logic value of 0, and the amorphous phase thereof corresponds to a reset state or has a logic value of 1.
To change the phase of the PRAM into the amorphous phase, the PRAM is heated to a temperature greater than a melting temperature of the PRAM and rapidly cooled down. To change the phase of the PRAM into the crystalline phase, the PRAM is heated to a temperature lower than the melting temperature for a predetermined time.
A key point to the PRAM is that it is formed of a phase-change material such as chalcogenide. In general, the phase-change material is a GST alloy composed of germanium (Ge), antimony (Sb), and tellurium (Te). When the GST alloy is heated or cooled, its state rapidly changes between the amorphous state (reset state) and the crystalline state (set state), that is, its logic value is switched between 1 and 0. Therefore, the GST alloy is useful as a material for a PRAM memory device.
To write data to a memory cell of the PRAM, the chalcogenide is heated to a temperature equal to or greater than its melting temperature and rapidly cooled down to place the chalcogenide in an amorphous state. Otherwise, chalcogenide is heated at a temperature less than the melting temperature, maintained at the temperature, and cooled to change the chalcogenide into a crystalline state.
FIG. 1 is a circuit diagram of a conventional phase-change memory cell 10 disclosed in U.S. Pat. No. 5,883,827. The memory cell 10 includes a phase-change variable resistance device R1, a first terminal of which is connected to a bit line BL and a second terminal of which is connected to a drain of a selection transistor N1, and the selection transistor N1 whose gate is connected to a word line WL and whose source is connected to a reference voltage VSS.
FIG. 2 is a circuit diagram of a phase-change memory array 100 comprising a plurality of phase-change memory cells 10 equivalent to the phase-change memory 10 of FIG. 1. The plurality of phase-change memory cells 10 are connected to a bit line BL which is connected to a sense amplifier (not shown).
The PRAM has lately attracted considerable attention as a next-generation memory. However, integrity of the PRAM needs to be improved in order for the PRAM to be competitive with other types of memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and flash memory.
As described above, data is written to the PRAM by heating the PRAM using Joule heat. However, there is a restriction to reducing a size of a control transistor of a conventional memory cell, which supplies current required to generate the Joule heat, thereby preventing an increase in the integration density of the PRAM.
Accordingly, there is a growing requirement for a cell structure that can increase the integration density of the PRAM and an improvement of the configuration of a semiconductor memory device using the improved cell structure.